ASIC RTL Design Intern

What to Expect

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities.

Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

The Tesla AI Hardware team is looking for a RTL Design Graduate Intern to work on industry leading AI accelerators. Candidate is expected to implement and document microarchitecture specifications, define system-level functional requirements, and deliver high quality design to achieve project targets.

What You’ll Do What You’ll Do

• Micro-architecture specification and design.
• Deliver Performance, Area and Power-efficient RTL design.
• Specification, microarchitecture, and RTL design of complex subsystems and SOC.
• Work with the architecture and software teams to achieve design targets.
• Balance performance, power, safety, and cost requirements.
• Trade-off functional, physical and performance requirements.
• Work with cross-functional teams, including implementation, verification, and performance engineers.
• Design for synthesis.

What You’ll Bring What You’ll Bring

• High performance (low latency, high bandwidth) design techniques
• Area and power-efficient complex RTL design
• Low power microarchitecture techniques
• Verilog RTL logic design.
• Experience with simulators and waveform debug tools.
• Knowledge of logic design principles, including timing and power implications.
• Degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• Fresh Graduates are welcome
• Relevant internship experience is a plus
• Familiarity with relevant IEEE standards and hardware interfaces is a plus.
• Experience with high speed SERDES or SOC design is a plus.