
Inventing the technologies the world loves.
STA Design Engineer - Static Timing Analysis - Cork, Ireland
必备技能
Python
Company:
QT Technologies Ireland Limited:
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:Job Description
As a Qualcomm STA Engineer, you will perform static timing analysis, develop timing constraints, and optimize timing performance for a variety of high-performance, high-quality, low-power world-class products. You will collaborate with cross-functional teams to ensure timing closure and validate timing models, contributing to the successful execution of product development.
The STA team at Qualcomm is responsible for evaluating block-level and top-level timing to ensure optimal performance and power efficiency in advanced cores and SOCs. As a STA Engineer, you will conduct static timing analysis on gate-level PNR netlists, provide feedback to RTL, Synthesis and Physical Design teams to improve PPA, collaborate with cross-functional teams to meet timing constraints, and produce timing ECOs to resolve violations. Your role is crucial in developing high-performance, low-power ASIC solutions that drive the future of technology.
**Please note this role will require 5 days per week onsite in our Cork office
You Will Be Responsible For:
You will be a member of a team working on timing signoff for Snapdragon Cores and SOCs, methodologies and flows:
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Performing STA and timing closure for complex cores and full-chip SOCs
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Enhancing techniques and methodologies for STA and timing closure
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Driving accuracy of timing closure and static/dynamic flows to reduce turnaround time
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Ensuring compliance with timing signoff checklists and criteria
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Automation for timing and power data mining and processing
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Participating in project proposal development including key milestones and deliverables
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Executing and delivering project goals in a timely manner with production support
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Resolving issues in all phases of development to ensure smooth project execution
We Would Love To See:
-
Expertise in STA tools (Prime Time, Prime Shield or Tempus) used for hierarchical analysis in large So Cs
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Hands-on experience with Tweaker, Prime Closure, PTECO, or Tempus ECO for timing closure
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Highly proficient in automation: Python, TCL or Perl
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Strong knowledge of ASIC design flows (RTL-to-GDS)
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Interest in Design for Parametric Yield is an added advantage
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Comfortable with extraction, circuit simulation tools and environments is a plus
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Excellent problem-solving skills and result-driven approach, able to work and drive practical solutions under research environment.
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Good communication and personal skills in a multi-disciplinary, fast-paced engineering environment
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4+ years of related work experience
Where you will be working
Cork has a proud reputation as Ireland's second largest economic engine and is now one of the Top 20 location choices in Europe with 39,000 people being employed by over 170 overseas companies.There's a growing diversity in the region with people from many nationalities relocating to Cork, relishing the opportunity to work and live in a location that offers an excellent quality of life.
A gateway to Europe, Cork airport provides access to almost 50 international destinations including transatlantic air routes.
Equal Opportunities
We are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any protected classification.
What's on Offer:
Apart from working in an open, relaxed and collaborative space, you will enjoy:
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Salary, stock and performance related bonus
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Maternity/Paternity Leave
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Employee stock purchase scheme
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Matching pension scheme
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Education Assistance
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Relocation and immigration support (if needed)
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Life, Medical, Income and Travel Insurance
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Subsidised memberships for physical and mental well-being
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Bicycle purchase scheme
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Employee run clubs, including, running, football, chess, badminton + many more
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers.
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关于Qualcomm

Qualcomm
PublicInventing the technologies the world loves.
10,001+
员工数
San Diego
总部位置
$136B
企业估值
评价
3条评价
3.0
3条评价
工作生活平衡
3.0
薪酬
2.0
企业文化
2.5
职业发展
3.5
管理层
2.0
45%
推荐率
优点
Opportunity to work at reputable company
Interesting work and new skill development
Strong brand name recognition
缺点
Low compensation compared to market rates
Poor communication from employees
No benefits provided
薪资范围
21个数据点
Mid/L4
Mid/L4 · Analog Mixed Signal Design Engineer
4份报告
$155,284
年薪总额
基本工资
$119,434
股票
-
奖金
-
$155,284
$155,284
面试评价
8条评价
难度
2.8
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
常见问题
Coding/Algorithm
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
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