Senior Bench Test Engineer, HSIO

This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs ( System on Chip) designed by Qualcomm.

Main responsibilities includes defining and executing the development of Test methodologies and characterization of High Speed SERDES Interfaces such as PCIe, USB4, UFS, DP, MIPI(DSI,CSI), PLLs and leading edge LP-DDR & PC-DDR Subsystem components (DRAM, DRAM Controller, Mixed Signal PHY IP, IOs, Clocking architecture, Delay circuits, Power Distribution Network) as well as other proprietary interfaces.

Responsibilities includes developing and executing characterization plans for High Speed Interfaces to optimize design parameters and validate electrical compliance, driving corresponding first silicon bring up & debug to qualify designs fabricated at external foundries and performing technical data analysis of parametric performance over various operating conditions and configurations.

Engineer will also assist in HW design and debug power integrity (PI) and signal integrity(SI) issues related to package and board design. Engineer will be working closely with cross-functional teams such as IC Design, Systems Engineering for chip/circuit bring up and debug. Engineer will be working with Customer Engineering and Hardware Applications teams to resolve customer issues/RMA debug in a time critical environment. The individual selected for the position should be passionate about delivering quality work products, seek to continually learn about Qualcomm products as well as essential knowledge of industry trends, competitor products, and advances in various engineering fields from publicly available information and assist in conducting specialized analyses (e.g., feasibility studies, signal integrity, teardown analyses).

Must have skill:

• 5+ years in High Speed Silicon Validation

Preferred Qualifications

• Good understanding of VLSI technologies, CMOS analog and digital integrated circuits, mixed-signal and semiconductor physics.
• Knowledge of High Speed test and characterization including eye diagram characteristics, Receiver JTOL performance, Jitter analysis, signal integrity etc.
• Familiarity with SERDES Transmitter/Receiver design blocks.
• Hands on experience with lab equipment such as Oscilloscopes, TDRs/VNAs, J-BERT etc.
• Experience with Python/C# for test automation.
• Familiarity with Board Design concepts(Schematic reviews, Layout best practices etc) is a plus.
• Good ASIC device level characterization skills. System level knowledge is a plus.
• Strong verbal and written communications skills as well as good organization and documentation skills.
• Strong problem solving & debugging skills. Ability to work independently and with good initiative to overcome technical challenges.
• Strong Interpersonal and teamwork skills with proven ability to work effectively in a fast-paced multi-disciplinary environment.