招聘
In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise
Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication So Cs.
Mandatory Knowledge/Skills/Abilities:
- Have prominent tracking record in modeling analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems.
- Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++.
- Have a decent understanding in CMOS analog / mixed-signal design.
Preferred Knowledge/Skill/Abilities:
- Able to create IBIS-AMI model.
- Can code in System-Verilog (WREAL).
- Able perform .LIB generation
- Fluent in verbal and written communications;
- Independently resolves issues and conquer design challenges;
- Self-motivated and detail-oriented;
- Has the knowledge of (optical) communication theories and Matlab coding.
Education and Experience Requirements:
-
Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience
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Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance.
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Perform the functional verification and timing analysis on the IPs and the blocks.
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Work with the digital verification team to generate an adequate interface to ensure the robustness of the design.
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关于Nokia

Nokia
PublicNokia Corporation is a Finnish multinational telecommunications, information technology, and consumer electronics corporation, originally established as a pulp mill in 1865.
10,001+
员工数
Espoo
总部位置
$24B
企业估值
评价
3.6
10条评价
工作生活平衡
4.2
薪酬
3.5
企业文化
4.0
职业发展
2.8
管理层
2.5
65%
推荐给朋友
优点
Good work-life balance and flexibility
Supportive and relaxed work environment
Great culture and people
缺点
Frequent layoffs and job security issues
Limited career advancement opportunities
Constant leadership and priority changes
薪资范围
28个数据点
Junior/L3
Mid/L4
Junior/L3 · Global 1830 TAC Engineer
1份报告
$141,314
年薪总额
基本工资
$108,703
股票
-
奖金
-
$141,314
$141,314
面试经验
4次面试
难度
3.0
/ 5
时长
14-28周
录用率
25%
体验
正面 50%
中性 25%
负面 25%
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Interview
4
HR Follow-up
5
Offer
常见问题
Technical Knowledge
Coding/Algorithm
Behavioral/STAR
Past Experience
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