The successful candidate will design and validate high‑speed packages through EM simulation, signal/power integrity analysis, and correlation with lab test & measurement verification. In addition, you will develop and maintain ADKs across multiple EDA platforms, including rule decks, parameterized cells, technology files, and automated verification flows.

You Have:

• Ph.D. degree in Electrical Engineering or Physics with minimum of 4 years of industry experience (or MSEE with 8 years)

• Expertise in 2.5D/3D EM component design, including interconnect, with simulation and analysis software (Cadence, Keysight ADS, 3DS CST or ANSYS HFSS, etc.)

• Expertise in package design software (Cadence Allegro X APD, Siemens Xpedition, etc.)

• Experience with developing PDKs/ADKs in EDA CAD tools (Cadence, Keysight, etc.)

• Knowledge of IC packaging materials & techniques, substrate design, and microelectronics assembly process flows

• Experience with SI/PI simulation and analysis software

• Advanced knowledge of RF & Optoelectronics test & measurement equipment

Nice to Have:

• Expertise in PCB technology, including schematic capture and layout design (Altium Designer, etc.)

• Experience with RF component design (filters, couplers, equalizers, transitions)

1. Design, Modeling, and Verification

• Perform high‑speed package design for advanced heterogenous packages (e.g., SiP, FC‑BGA, 2.5D/3D, chiplets) for high-speed RF and Optoelectronics.
• Build and refine 3D EM models of package structures (transmission lines,interconnect and EM passives, etc.).
• Run and interpret EM, SI, and PI simulations (S‑parameters, TDR/TDT, eye diagrams, crosstalk, impedance, PDN impedance).
• Define and validate routing topologies and stackups to meet timing, loss, crosstalk, and impedance requirements.
• Collaborate with silicon, board, and system teams to co‑optimize package, die, and PCB for end‑to‑end performance.
• Correlate simulation results with lab measurements (VNA, TDR, high‑speed scopes) for model validation and sign‑off.

1. ADK, EDA Flows, and Automation

• Develop and maintain Assembly Design Kits (ADKs) for package design across multiple EDA tools and foundry/OSAT technologies.
• Create and validate technology files, layer stacks, material properties, and design rule sets for package implementation.
• Develop DRC/LVS/validity rule decks for package layouts and ensure consistency across tools and process nodes.
• Build parameterized cells (PCells) and reusable library components for common package elements (vias, bumps, pads, RDLs, etc.).
• Implement scripted flows (e.g., Python, AEL, SKILL, etc.) to automate design entry, simulation setup, and verification.
• Integrate version control, configuration management, and documentation for ADKs and EDA flows.