Senior RTL Design Lead

Job Summary

RTL Design Engineers design and develop digital hardware blocks using HDLs such as Verilog/System Verilog/VHDL for ASIC or FPGA projects

Key Responsibilities

• Develop RTL code for digital IPs, So Cs, and subsystems

• Create microarchitecture specifications from system requirements

• Optimize designs for area, power, and performance

• Perform linting, CDC, and synthesis checks

• Collaborate with DV, DFT, and Physical Design teams

• Debug functional issues and timing-related problems

• Support FPGA prototyping and silicon bring-up

Skill Requirements

• Verilog/System Verilog/VHDL

• Digital design fundamentals

• FSMs, pipelines, memories, buses, clocking concepts

• Scripting: Python/Perl/TCL/Shell

• Tools: Synopsys DC, Spy Glass, Verdi, VCS

Other Requirements

• AMBA protocols (AXI/AHB/APB)

• Low-power design concepts (UPF/CPF)

• ASIC/FPGA flow understanding