Senior Designer

Job Summary

Experience with Cadence APD IC Package/substrate Design experience Good experience with Flip Chip and Wire Bond designs Worked from Die pin list to Tape out Good understanding of package fabrication and assembly rules related to flip chip designs.Exposure to different package technologies such as MCM, flip chip / wire bond, 3D, 2.5D etc., added advantage Should have experience in working with High-speed interfaces such as PCIe, LPDDRx, GDDR, XGMII, etc.,Good knowledge and understanding in Signal Integrity and Power Integrity requirements Should be able to work with customer SPOC independently.Good Exposure to Stackup design, DFM, DFA rules and adherence.Experience with Cadence APD IC Package/substrate Design experience

Key Responsibilities

Signal Integrity tool Expert Specifically, in Cadence Sigrity 2.5D and 3D-EM and Agilent ADS.Power Integrity tool Expert Specifically, in Cadence Sigrity 2.5D and 3D-EM and Hspice.Allegro tool Knowledge Basic knowledge in Viewing/Understanding the routing details and extracting quick reports.Lab measurement equipment Good Familiarity with Vector Network Analyzer (VNA) and Oscilloscopes.

Skill Requirements

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Other Requirements

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