[HW] NoC (Network-on-Chip) Design Engineer

Frontier of On-device AI Semiconductors

for Everyone, Everywhere

About DeepX Co., Ltd.

DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.

By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.

Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO

opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.

We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link

★ If you want to be part of world-class innovation? Please talk with us.

★Explore our journey: The DEEPX White Paper ☞ Link

Responsibilities

• Design and implement NoC architecture for high-performance AI accelerators.

• Optimize on-chip interconnects for power, performance, and area (PPA).

• Conduct performance modeling and simulation to analyze throughput, latency, and congestion.

• Work closely with Architecture and Frontend teams to define bus protocols and interface specifications.

• Perform RTL coding, synthesis, and timing closure for NoC components.

• Develop verification strategies to ensure the robustness and scalability of the NoC design.

Qualifications

• Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.

• Proven experience in RTL design (Verilog/System Verilog) for complex SoC environments.

• In-depth understanding of on-chip communication protocols (e.g., AMBA AXI, ACE, CHI).

• Experience with NoC architecture concepts such as routing algorithms, flow control, and arbitration logic.

• Strong analytical skills for performance bottleneck identification and resolution.

• Excellent communication skills and the ability to work in a fast-paced, collaborative environment.

Preferred Qualifications

• Experience with commercial NoC IP (e.g., Arteris, Net Speed/Sifive) or in-house custom NoC development.

• Knowledge of AI/Machine Learning hardware acceleration and data flow requirements.

• Proficiency in scripting languages such as Python, Perl, or Tcl for design automation.

• Experience in power-aware design (UPF/CPF) and clock domain crossing (CDC) analysis.

• Familiarity with performance simulation tools (e.g., SystemC, gem5).

Recruitment Process

• Application Review - (Phone Interview) - Technical Interview
• Organizational Culture Fit Interview
• CEO Interview
• Reference Check / Compensation Discussion

※ The recruitment process may vary depending on the position and application content.

※ Candidates with less than 3 years of experience are required to submit their academic transcripts.

Employment Type

• Full-time (3-month probationary period with 100% compensation)

Working Hours

• Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)

Notes

• If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.

• A 3-month probationary period applies after joining, with no reduction in salary or benefits.

Benefits

• 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여

• 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)

• 점심식사 + 아침 & 저녁식사 지원

• 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공

• 사우나가 포함된 피트니스 비용 지원

• 연 1회 종합건강검진 지원 (배우자 포함)

• 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공

• 설/추석 명절 상여금 지급

• 축하와 위로를 위한 경조휴가 및 경조금 지원