ポジションについて
Responsibilities:
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High speed interface design (TX/RX, equalization, clocking) for traditional Ser Des or chiplet interconnects.
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Evaluate and drive implementation of technology features for high-speed interface, including electrical performance optimization and reliability enhancement.
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2.5D/3DIC channel modeling.
Requirements:
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Education: Masters or PhD in Electrical Engineering (or similar)
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Must be fluent in English communication, both written and oral
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Must have more than 3 years of relevant industry experience in high-speed interface designs (larger or equal to 10Gbps).
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Understanding of high-speed interface architecture from theory, circuit design to silicon validation.
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Familiarity with EM extraction is preferred.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
