Lithography Engineer, OPC, Terafab

What to Expect

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.

Process engineering is where Terafab technology gets built, atom by atom, and lithography will define the limit of what we can build. You will develop and own patterning processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory. With mask production in-house, you'll have unprecedented feedback loops to co-optimize reticle and scanner strategies.

You should have deep expertise in optical lithography, but be ready to work across core process domains such as etch, metrology, and film deposition as integration evolves. This is a highly hands-on role at one of the most ambitious fab programs in the world.

What You’ll Do

• Develop Optical Proximity Correction for advanced-node and specialty layers across logic, memory, and space-hardened products
• Advance Resolution Enhancement Techniques to improve pattern fidelity, process window, and manufacturability
• Build and optimize Source Mask Optimization, OPC recipes, and OPC models spanning mask, after-develop inspect, and after-etch inspect, including model QC
• Deliver computing-efficient full-chip layout correction using rigorous physics, software engineering, and machine learning
• Transfer OPC models and recipes into volume manufacturing and sustain them through node and product ramps
• Calibrate and validate models against wafer and reticle data, using in-house mask production for tight mask-to-wafer feedback
• Analyze patterning issues with CD metrology, SEM review, and lithography simulation, then drive model and recipe corrections
• Support tapeout and model-release cycles, including rapid response to critical correction and verification issues

What You’ll Bring

• Degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Materials Science, Computer Science, Chemistry, Optics, Physics, Mathematics, or a related technical field, or equivalent experience
• 3+ years of OPC, RET, or computational lithography experience in a semiconductor fab, foundry, or EDA environment
• Hands-on experience developing OPC models, recipes, and QC methods for mask, ADI, and AEI
• Proficiency with industry EDA and OPC platforms such as Synopsys, Siemens, Cadence, or Brion
• Strong programming skill in Python, TCL, Perl, C, or C++ for flow automation and full-chip correction
• Working knowledge of EUV and Ar Fi lithography fundamentals, including optics, diffraction, and resist behavior
• Experience with lithography simulation tools such as Sentaurus Litho, Pro Lith, or equivalent
• Ability to work closely and proactively across lithography, mask, integration, design, and tapeout teams