Machine Learning Engineer, SI CoDesign

What to Expect

Our team designs, trains, and deploys large-scale neural networks optimized for inference on compute-constrained edge devices (CPU / GPU / custom AI ASIC). This role sits at the intersection of ML modeling and hardware-aware systems engineering — you will architect and train state-of-the-art models while co-designing them with the underlying silicon and compiler stack to maximize performance. You will drive the full lifecycle from model research and training at scale to quantized, latency-optimized deployment across Tesla's heterogeneous compute platforms.

What You’ll Do

• Design, train, and iterate on neural network architectures for autonomous driving and robotics, with a focus on efficiency-aware model design (architecture search, distillation, pruning, quantization-aware training)
• Co-design model architectures with compiler and ASIC teams to exploit hardware-specific capabilities (custom ops, dataflow patterns, memory hierarchy)
• Develop and optimize the model lowering and deployment pipeline from Py Torch to edge inference on Tesla's in-house AI ASIC
• Profile and optimize end-to-end inference latency and throughput across heterogeneous compute targets
• Implement custom CUDA / GPU kernels for training, post-processing, or operations not natively supported by frameworks
• Collaborate with AI teams on translating modeling breakthroughs into production-ready, hardware-efficient implementations

What You’ll Bring

• Strong foundation in deep learning, hands-on experience designing, training, and debugging neural network architectures (transformers, convnets, diffusion models, etc.)
• Proficiency with Py Torch (or equivalent framework), including distributed training, custom autograd ops, and mixed-precision workflows
• Proficiency with Python and C/C++ (modern C++17/20 preferred)
• Solid understanding of computer architecture and systems concepts (memory hierarchy, instruction pipelines, accelerator design)
• Experience with model optimization techniques: quantization, pruning, knowledge distillation, or neural architecture search
• Experience with CUDA or GPU kernel development
• Familiarity with ML compiler stacks or model lowering toolchains (e.g., TVM, XLA, MLIR, TensorRT) is a plus