Silicon Validation Engineer, SI Hardware

What to Expect

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

Tesla is building the silicon that powers Autopilot, Optimus, and the world's largest AI training clusters. The AI Hardware team designs every transistor in-house — and every high-speed link on those chips must work at the edge of physics before a single vehicle or robot ships. We are looking for an IP Characterization Engineer to own post-silicon electrical characterization of the interfaces that move data across our custom So Cs.

The Tesla AI Hardware team designs custom silicon for Autopilot, Optimus, and Tesla's AI training and inference systems. This role owns post-silicon electrical characterization of the high-speed interfaces that move data on those chips: PCIe, UFS, and DDR/LPDDR.

You will live in the lab. You will write the electrical test plans, run the scope/BERT/VNA measurements, extract margins across PVT, correlate silicon to simulation and ATE, and feed results back into PHY, package, board, firmware, and production test. When something is wrong at the electrical level, you are the person who finds it, proves it, and drives the fix — from first silicon through production sign-off.

The role will focus on developing Post-Silicon validation plan, tools, and infrastructure for Tesla’s custom So Cs and Platforms designs. As a Silicon Validation Engineer, the candidate will take on challenges like validating High-Speed Serdes, perform system level power characterization, and troubleshooting complex hardware bugs and field returns. The candidate will regularly take part in hardware design and schematics review, firmware development, and building automated test infrastructures for running large volume of post silicon system level tests. The candidate will also possess good system-level and architectural knowledge and some experience with DFT and PDE work.
What You’ll Do

• Own electrical characterization of PCIe Gen5/Gen6, UFS (M-PHY HS-Gx), and LPDDR5x/LPDDR6 from first silicon through production sign-off
• Write and execute electrical and analog validation plans: Tx/Rx compliance, eye/mask, bathtub, jitter, BER/FBER, insertion/return loss, equalization, training, and system-level margining
• Characterize PHY analog performance and link margin across process, voltage, and temperature; define operating windows and production guard bands
• Bring up first silicon in the lab: link training, LTSSM / M-PHY gear switching, memory training and margining, debug electrical and functional failures to PHY, package, board, firmware, or ATE root cause
• Perform end-to-end measurements with high-bandwidth real-time oscilloscopes, BERT, VNA, TDR, protocol/logic analyzers, and protocol exercisers; apply de-embedding, S-parameters, and channel correlation
• Correlate bench, system, and ATE results; close gaps that would otherwise surface as yield, interoperability, or field issues
• Partner with mixed-signal/PHY design, SI/PI, package and board, firmware/BIOS, diagnostics, ATE, and quality teams to drive root cause and design feedback
• Automate instrument control, data collection, and analysis in Python and/or using agentic AI workflows; present characterization data to technical forums and program reviews
• Influence pre-silicon testability — DFT hooks, loopback modes, observability — and validation-board requirements so post-silicon electrical work is actually executable

What You’ll Bring

• 5+ years of post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
• Hands-on ownership of PCIe or Ethernet Ser Des characterization, with additional experience in UFS or LPDDR5
• Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers — you have personally captured eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
• Working knowledge of signal integrity, Ser Des and single-ended memory PHY behavior, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specifications
• Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware failures
• Scripting for lab automation and data analysis (Python preferred)
• Clear written and verbal communication; you can present a margin plot and a root-cause story to design and program teams