Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We’re looking for a Physical Design Engineer – EMIR to join our silicon team. In this role, you’ll lead EM and IR-drop simulations to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. You’ll work with RTL, physical design, and analysis teams to implement power grid strategies that optimize performance, power, and area (PPA), particularly at advanced nodes like 7nm and below. You’ll also support EMIR sign-off and waiver methodologies across the chip hierarchy.

This role ishybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A physical design specialist with deep experience in EMIR analysis and signoff.

• Comfortable navigating advanced technology nodes and power integrity challenges.

• Proactive and detail-oriented, with a passion for pushing performance and reliability boundaries.

• Collaborative and effective across teams working on RTL, physical design, packaging, and reliability.

What We Need

• 7+ years of experience in physical design or signoff, with a focus on EMIR.

• Hands-on with Red Hawk, Voltus, or equivalent industry-standard EMIR tools.
  Strong understanding of IR-drop mitigation, EM compliance, and power grid design.

• Proficiency with layout extraction flows, RC modeling, and metal density checks.

• Experience working in advanced nodes (7nm, 5nm, 3nm), and with scripting languages like TCL, Python, Perl, or Shell.

• Knowledge of floorplanning, bump/RDL design, and sign-off flows (DRC/LVS, timing closure).

What You Will Learn

• How to architect and analyze robust power delivery for Tenstorrent’s RISC-V CPUs and AI chips.

• How to integrate EMIR signoff into fast-paced, high-performance chip design cycles.

• Best practices for hierarchical analysis and EMIR methodology across pre- and post-layout flows.

• Cross-functional collaboration for optimizing PPA while meeting stringent reliability goals.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.