トレンド企業

Semtech
Semtech

Semiconductor company

Staff Digital Engineer

職種エンジニアリング
経験Staff+
勤務地IND - Hyderabad, India
勤務オンサイト
雇用正社員
掲載2ヶ月前
応募する

必須スキル

SystemVerilog

Verilog

VHDL

Python

Perl

tcl

Digital IC design

RTL design

Timing closure

Low-power design

Responsibilities:

  • Define, develop, verify and optimize complex digital circuits for low-power mixed-signal circuits. Design digital hardware functions and sub systems in RTL code using System Verilog, Verilog or VHDL. Collaborate with system design to create digital specification definition. Implement design for testability (scan chain, BIST, boundary scan) and diagnosis features to support hardware testing. Generate technical documentation and participate in design reviews. (40%)

  • Support constraints definition, logic synthesis, and physical design for timing closure, DFT insertion and test vectors creation, static timing closure. (15%)

  • Support development of comprehensive verification plans and testbenches, including functional verification, RTL and gate-level simulations, timing analysis, and top verification. Participate in pre-silicon digital hardware emulation and FPGA prototyping. (15%)

  • Support silicon lab evaluation, performance characterization and debug. (10%)

  • Interface with system, embedded firmware, analog, verification and cross functional teams. (10%)

  • Technical support to test, product and application engineers. (10%)

Minimum Qualifications:

  • 4+ years of industry experience in digital integrated circuit design

  • B.S. or M.S. in Electrical or Computer Engineering

  • Strong analytical, synthesis and problem solving skills

  • Solid knowledge and experience in digital IC development, frontend-to-backend flow, timing closure, data path, signal processing, low-power techniques, basic constraints development, timing analysis, system trade-offs (power, speed, hardware resources, area)

  • Background with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, digital micro-architecture, interfaces, and dedicated hardware peripherals

  • Proficiency in System Verilog/Verilog/VHDL, scripting languages (Python, Perl, tcl), debugging capabilities, and industry leading digital EDA tools (Synopsys, Cadence, Siemens)

  • Knowledge of verification methodologies and tools (System Verilog, UVM/OVM, formal verification)

  • Demonstration of technical ownership and successful execution

  • Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)

  • Independent, self-motivated, rigorous, team player and able to follow through

  • Excellent verbal and written communication skills

Desired Qualifications

  • Digital development for mixed-signal ICs

  • Hands-on experience with development boards, FPGAs, logic analyzers, oscilloscopes, supplies, multimeters and the associated measurement methods

  • Knowledge of system-level aspects: signal processing, embedded firmware, analog, modelling, test and application

  • Experience with system design methods & tools, Matlab, etc.

  • Experience with consumer and/or ITA market circuit developments

閲覧数

1

応募クリック

0

Mock Apply

0

スクラップ

0

Semtechについて

Semtech

Semtech

Public

Semtech Corp supplies analog, mixed-signal semiconductors, and algorithms for enterprise, communication, and industrial applications.

1,001-5,000

従業員数

Camarillo

本社所在地

$1.2B

企業価値

レビュー

10件のレビュー

3.7

10件のレビュー

ワークライフバランス

3.2

報酬

3.8

企業文化

4.1

キャリア

2.5

経営陣

2.3

65%

知人への推奨率

良い点

Supportive and friendly coworkers/team

Good benefits and pay

Flexible work arrangements

改善点

Limited career advancement/upward mobility

Poor management and leadership direction

Heavy/overwhelming workload

給与レンジ

41件のデータ

Mid/L4

Principal/L7

Senior/L5

Mid/L4 · SAP APO Business Analyst

2件のレポート

$92,738

年収総額

基本給

$80,642

ストック

-

ボーナス

-

$90,850

$94,628

面接レビュー

レビュー1件

難易度

2.0

/ 5

期間

14-28週間

面接プロセス

1

Application Review

2

HR Screen

3

Hiring Manager Interview

4

Skills Assessment

5

Offer

よくある質問

Past Experience

Technical Knowledge

Attention to Detail

Data Management Skills

Culture Fit