Photonic Integrated Circuit - Wafer level Burn-in Engineer

We engineer Photonic Integrated Circuits (PICs) end to end - design, development, and rigorous testing - inside a truly vertically integrated model. Join Nokia Network Infrastructure (NI) California as PIC Test Development Engineer, creating and implementing SW and HW solutions for both R&D and large throughput, production level testing of complex PICs! Partnering closely with internal manufacturing and leveraging our own world-class wafer fabs, we translate cutting edge photonics into production grade optical modules that power the next generation of optical networks and interconnects of AI applications.

NION2026

• PhD. in  Electrical Engineering, Applied Physics, or equivalent with minimum of 3 years of applicable graduate-level and/or industrial experience in optical communications or photonics, or Master’s degree with 3+ years of applicable industry experience.

• Fundamental understanding of active and passive semiconductor optoelectronic device characteristics (e.g. semiconductor lasers/amplifiers, photo diodes, modulators, waveguides)

• Hands-on experience with semiconductor electrical and optical characterization techniques (e.g. diode characterization, laser threshold, spectral measurements, optical power measurements. Experiences with wafer probing is a plus

• Software development skills and strong drive for test automation and data analysis. Programming experience in Matlab, C, C++, Python, LabVIEW, VB.net or similar for automation of instrument control and data acquisition is a plus

• Ability to build, maintain and troubleshoot complex test hardware and software in a cross-functional environment

• Experience with a production level test environment (including Gage RR, SPC, tool qualification) is a plus.

• Experience with database tools like JMP, SQL is a plus.

• Attention to detail and willingness to produce detailed documentation

• Ability to work within a team environment, clearly and concise communication inside and outside the Test team

HOW YOU WILL CONTRIBUTE AND WHAT YOU WILL LEARN

• Lead wafer level PIC Burn-in development. Work with vendor complete wafer Burn-in hardware and process development

• Lead efforts developing fully wafer level PIC test and Burn-In solutions

• Design test plans and algorithms of wafer level PIC performance validation tests

• Extensive test station qualification work, including Gage RR and statistical process control (SPC)

• Thorough documentation of all test solutions and communication to other teams and outside vendors