About the job

In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs.

• Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis.

• Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces.

• Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations.

• Use AI techniques for faster and optimal physical design convergence -timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.

Minimum qualifications

• PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience.

• Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools.

• Experience with accelerator architectures and data center workloads.

Preferred qualifications

• 2 years of experience in Silicon domain post PhD.

• Experience with performance modeling tools.

• Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies.

• Knowledge of high performance and low power design techniques.