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Principal Product Engineer - Quantus

Cadence

Principal Product Engineer - Quantus

Cadence

GYEONGGI-DO (Seoul)

·

On-site

·

Full-time

·

1w ago

Required Skills

Parasitic extraction

Transistor-level extraction

Cell-level extraction

Analog design

Physical verification

Simulation

RC correlation

Communication

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

The Product Engineering team collaborates closely with customers, foundries, R&D, Marketing, and Application Engineers to develop solutions that address our customers’ unique and complex design challenges. We are seeking a PEX (RC Parasitic Extraction) Product Engineer to support foundry design enablement kits and to deliver Cadence PEX tool solutions in a timely and professional manner. The candidate will work both on-site and off-site.

Key Responsibilities:

  • Act as the primary interface between customers and corporate R&D for all PEX‑related issues.
  • Develop extraction Techfiles for strategic partners.
  • Evaluate and qualify extraction Techfiles using provided testcases.
  • Establish efficient flows to improve PEX tool quality and product performance.
  • Execute expert-level benchmarks and resolve complex customer issues.
  • Collaborate with R&D, field teams, customers, and foundries to define product requirements and enhancements.
  • Work closely with headquarters R&D and Product Engineers across global sites to resolve technical issues.

Requirements

  • 9+ years of Extraction experience with Bachelor’s degree in electrical engineering is required, Master’s degree is preferred.
  • Strong background in transistor-level and cell-level parasitic extraction, with solid understanding of cell-level and analog design.
  • Hands-on experience with industry PEX tools such as StarRC or QRC.
  • Experience with extraction in advanced technology nodes.
  • Knowledge and experience with physical verification tools (e.g., PVS/Pegasus, Calibre, ICV) required.
  • Knowledge and experience with Simulator tools (e.g., HSPICE, Spectre..)
  • Knowledge of RC correlation and delay on design data.
  • Good communication skills internally with team members and externally with customers.
  • Work experience in-design service team would be advantageous.
  • Proficiency in spoken and written English.
  • Programming experience in Tcl, Perl, Python, or SKILL is a plus

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About Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

Employees

San Jose

Headquarters

Reviews

3.3

7 reviews

Work Life Balance

2.0

Compensation

2.5

Culture

1.8

Career

2.0

Management

1.5

15%

Recommend to a Friend

Pros

Built strong client relationships

Useful for repetitive tasks

Employment opportunities

Cons

Poor management and micromanagement

Lack of career growth opportunities

Technical architecture and code quality issues

Salary Ranges

65 data points

Junior/L3

Junior/L3 · Data Analyst

1 reports

$91,103

total / year

Base

$85,276

Stock

-

Bonus

$5,827

$59,612

$139,984

Interview Experience

1 interviews

Difficulty

3.0

/ 5

Duration

14-28 weeks

Interview Process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

Common Questions

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving