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Semtech
Semtech

Semiconductor company

Sr. Staff Digital Engineer

职能工程
级别Staff+
地点IND - Hyderabad, India
方式现场办公
类型全职
发布2个月前
立即申请

必备技能

SystemVerilog

Verilog

VHDL

Digital IC design

Logic synthesis

Timing closure

Python

Perl

tcl

UVM

Formal verification

Responsibilities:

  • Define, develop, verify and optimize complex digital circuits for low-power mixed-signal circuits. Design digital hardware functions and sub/full systems in RTL code using System Verilog, Verilog or VHDL. Collaborate with system design to create digital specification definition. Implement design for testability (scan chain, BIST, boundary scan) and diagnosis features to support hardware testing. Generate technical documentation and drive design reviews. (40%)

  • Define constraints, perform logic synthesis, implement or supervise physical design for timing closure, perform DFT insertion and create test vectors, perform static timing closure. (10%)

  • Support development of comprehensive verification plans and testbenches, including functional verification, RTL and gate-level simulations, timing analysis, and top verification. Define and implement pre-silicon digital hardware emulation and FPGA prototyping. (20%)

  • Support silicon lab evaluation, performance characterization and debug. (10%)

  • Interface with system, embedded firmware, analog, verification and cross functional teams. (10%)

  • Technical support to test, product and application engineers. (10%)

Minimum Qualifications:

  • 10+ years of industry experience in digital integrated circuit design

  • B.S. or M.S. in Electrical or Computer Engineering

  • Strong analytical, synthesis and problem solving skills

  • In-depth knowledge and experience in digital IC development for mixed-signal ICs, frontend-to-backend flow, timing closure, HW-SW architectures and co-design, data path, signal processing, low-power techniques, constraints development, timing analysis, system trade-offs (power, speed, hardware resources, area)

  • Strong background with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, digital micro-architecture, interfaces, and dedicated hardware peripherals

  • Proficiency in System Verilog/Verilog/VHDL, scripting languages (Python, Perl, tcl), debugging capabilities, and industry leading digital EDA tools (Synopsys, Cadence, Siemens)

  • Knowledge of verification methodologies and tools (System Verilog, UVM/OVM, formal verification)

  • Demonstration of technical leadership and innovation

  • Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)

  • Hands-on experience with development boards, FPGAs, logic analyzers, oscilloscopes, supplies, multimeters and the associated measurement methods

  • Independent, self-motivated, rigorous, innovating, team player and able to follow through

  • Excellent verbal and written communication skills

  • Knowledge of system-level aspects: signal processing, mixed-signal, embedded firmware, analog, modelling, test and application

Desired Qualifications

  • Experience with system design methods & tools, Matlab, etc.

  • Experience with consumer and/or ITA market circuit developments

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关于Semtech

Semtech

Semtech

Public

Semtech Corp supplies analog, mixed-signal semiconductors, and algorithms for enterprise, communication, and industrial applications.

1,001-5,000

员工数

Camarillo

总部位置

$1.2B

企业估值

评价

10条评价

3.7

10条评价

工作生活平衡

3.2

薪酬

3.8

企业文化

4.1

职业发展

2.5

管理层

2.3

65%

推荐率

优点

Supportive and friendly coworkers/team

Good benefits and pay

Flexible work arrangements

缺点

Limited career advancement/upward mobility

Poor management and leadership direction

Heavy/overwhelming workload

薪资范围

41个数据点

Mid/L4

Principal/L7

Senior/L5

Mid/L4 · SAP APO Business Analyst

2份报告

$92,738

年薪总额

基本工资

$80,642

股票

-

奖金

-

$90,850

$94,628

面试评价

1条评价

难度

2.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

HR Screen

3

Hiring Manager Interview

4

Skills Assessment

5

Offer

常见问题

Past Experience

Technical Knowledge

Attention to Detail

Data Management Skills

Culture Fit