招聘
必备技能
DFT
ATPG
ASIC Design
Verilog
VHDL
Digital electronics
Tcl
Perl
Problem Solving
Communication
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Design Systems is looking for a highly motivated engineer to be part of the Modus R&D team, with a focus on validating and supporting Design-for-test (DFT) technologies. Candidate must have 7+ years of experience in DFT/ATPG/ASIC Design flows and knowledge of RTL Verilog/VHDL coding styles, Synthesis. This position requires excellent communication skills (written and oral) to interface with Product Engineers (PEs) and R&D and will occasionally also involve direct customer support responsibilities. Will work on complex problems that require innovative thinking, debugging customer reported problems and collaboration with R&D to propose out-of-box solutions with emphasis on robustness, PPA and scalability.
Role Responsibility
Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Boundary Scan, Compression, RTL DFT, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs. Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool. Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues. Debug issues reported by customers and suggest/implement measures to plug the gaps.
Position Requirements
Candidate is expected to be:
- B.E. in Electronics/Electrical
- Strong in Digital electronics, Verilog
- Good understanding of DFT techniques and methodologies
- Familiarity with Test standards like 1149.1, 1500, 1687 is a plus
- Experience with Cadence Test or other Test tools is preferred
- Good scripting skills (Tcl, Perl)
- Strong analysis and problem solving skills
- Good communication skills are a must
- Keen & quick learner ready to learn new things with little guidance & take up challenging tasks
Education: B. Tech/BE/M. Tech / M.E.
This position is in Product Validation Team of Cadence Modus DFT Software Solution.
Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design process.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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