
Semiconductor company
Sr. Staff Digital Engineer
필수 스킬
SystemVerilog
Verilog
VHDL
Digital IC design
Logic synthesis
Timing closure
Python
Perl
tcl
UVM
Formal verification
Responsibilities:
-
Define, develop, verify and optimize complex digital circuits for low-power mixed-signal circuits. Design digital hardware functions and sub/full systems in RTL code using System Verilog, Verilog or VHDL. Collaborate with system design to create digital specification definition. Implement design for testability (scan chain, BIST, boundary scan) and diagnosis features to support hardware testing. Generate technical documentation and drive design reviews. (40%)
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Define constraints, perform logic synthesis, implement or supervise physical design for timing closure, perform DFT insertion and create test vectors, perform static timing closure. (10%)
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Support development of comprehensive verification plans and testbenches, including functional verification, RTL and gate-level simulations, timing analysis, and top verification. Define and implement pre-silicon digital hardware emulation and FPGA prototyping. (20%)
-
Support silicon lab evaluation, performance characterization and debug. (10%)
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Interface with system, embedded firmware, analog, verification and cross functional teams. (10%)
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Technical support to test, product and application engineers. (10%)
Minimum Qualifications:
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10+ years of industry experience in digital integrated circuit design
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B.S. or M.S. in Electrical or Computer Engineering
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Strong analytical, synthesis and problem solving skills
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In-depth knowledge and experience in digital IC development for mixed-signal ICs, frontend-to-backend flow, timing closure, HW-SW architectures and co-design, data path, signal processing, low-power techniques, constraints development, timing analysis, system trade-offs (power, speed, hardware resources, area)
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Strong background with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, digital micro-architecture, interfaces, and dedicated hardware peripherals
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Proficiency in System Verilog/Verilog/VHDL, scripting languages (Python, Perl, tcl), debugging capabilities, and industry leading digital EDA tools (Synopsys, Cadence, Siemens)
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Knowledge of verification methodologies and tools (System Verilog, UVM/OVM, formal verification)
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Demonstration of technical leadership and innovation
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Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)
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Hands-on experience with development boards, FPGAs, logic analyzers, oscilloscopes, supplies, multimeters and the associated measurement methods
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Independent, self-motivated, rigorous, innovating, team player and able to follow through
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Excellent verbal and written communication skills
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Knowledge of system-level aspects: signal processing, mixed-signal, embedded firmware, analog, modelling, test and application
Desired Qualifications
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Experience with system design methods & tools, Matlab, etc.
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Experience with consumer and/or ITA market circuit developments
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Semtech 소개

Semtech
PublicSemtech Corp supplies analog, mixed-signal semiconductors, and algorithms for enterprise, communication, and industrial applications.
1,001-5,000
직원 수
Camarillo
본사 위치
$1.2B
기업 가치
리뷰
10개 리뷰
3.7
10개 리뷰
워라밸
3.2
보상
3.8
문화
4.1
커리어
2.5
경영진
2.3
65%
지인 추천률
장점
Supportive and friendly coworkers/team
Good benefits and pay
Flexible work arrangements
단점
Limited career advancement/upward mobility
Poor management and leadership direction
Heavy/overwhelming workload
연봉 정보
41개 데이터
Mid/L4
Principal/L7
Senior/L5
Mid/L4 · SAP APO Business Analyst
2개 리포트
$92,738
총 연봉
기본급
$80,642
주식
-
보너스
-
$90,850
$94,628
면접 후기
후기 1개
난이도
2.0
/ 5
소요 기간
14-28주
면접 과정
1
Application Review
2
HR Screen
3
Hiring Manager Interview
4
Skills Assessment
5
Offer
자주 나오는 질문
Past Experience
Technical Knowledge
Attention to Detail
Data Management Skills
Culture Fit
최근 소식
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