Company:

Qualcomm Semiconductor Limited:

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a forward-thinking technology company, Qualcomm advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.

We are seeking a seasoned DFT Engineer to join our SoC design team. In this role, you will be responsible for architecting and implementing Design-for-Test strategies across complex SoC designs, ensuring robust test coverage, manufacturability, and post-silicon validation. You will work closely with RTL, physical design, and verification teams to integrate scan, MBIST, boundary scan, and other test features into our advanced semiconductor products.

Responsibilities

• Define and implement DFT architecture including scan insertion, boundary scan, and MBIST
• Develop test strategies to meet coverage goals and manufacturing requirements
• Integrate DFT features into RTL and gate-level netlists
• Perform ATPG, fault simulation, and test coverage analysis
• Collaborate with physical design team to ensure DFT-friendly layout and routing
• Support bring-up and debug of test features in silicon
• Work with ATE teams to enable pattern generation and validation
• Drive methodology improvements and automation for DFT flow
• Provide guidance on RTL coding for testability and scan compliance
• Occasional business travel across APAC and other regions may be required

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years of hands-on experience in DFT architecture and implementation
• Proficiency in EDA tools such as Synopsys DFT Compiler, Tessent, Spy Glass DFT
• Experience with scan insertion, ATPG, MBIST, and boundary scan
• Familiarity with RTL-to-GDSII flow and test integration
• Strong scripting skills in Python, Tcl, or Shell
• Excellent problem-solving and cross-functional communication skills

Preferred Qualifications

• Experience with hierarchical DFT and large-scale SoC integration
• Knowledge of ISO 26262 or other safety-related test standards
• Familiarity with post-silicon validation and debug of test features
• Exposure to ATE pattern generation and silicon bring-up
• Experience with EDA tools such as Tessent, TestMAX, or Encounter Test
• Comfortable working in a globally distributed engineering environment
• Experience correlating pre-silicon test coverage with post-silicon yield

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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