Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary:

Physical implementation of industry leading integrated graphics core designs from RTL2GDS of very complex and high frequency blocks or top level. This includes synthesis, Place and Route which encompasses floor-planning, placement, clock implementation and routing of very high gate count design to meet very aggressive Power, Performance and Area (PPA) targets. The incumbent will work with the latest technology process nodes and employ advanced design techniques to push the PPA envelope. This role includes collaborating with RTL design teams to optimize designs. The incumbent will also collaborate with multi-disciplinary teams and tool vendors to develop and enhance automation in design flows and methodologies for improved efficiency. This role requires a comprehensive understanding of the trade-offs in Power, Performance, and Area (PPA) to make informed decisions that achieve the optimal design.

The ideal candidate will have/demonstrate the following:

• Experience in Physical design implementation which includes floor-planning, placement, clock implementation, routing for complex, high frequency designs
• Experience with physical synthesis and implementation tools
• Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus
• Must have good knowledge of static timing analysis, reliability and power analysis
• Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs
• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks
• Strong understanding of GPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance
• Solid working knowledge of scripting skills including tcl, perl or python
• Excellent communication skills and collaborating in a team environment is a must

Preferred Skills:

• Clock, power delivery network design, process technology, prior experience in flow and methodology development, block closure leading to successful tape-outs
• Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff
• Hands on experience working with very complex designs that push the envelope of Power, Performance and Area
• Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous
• Prior experience in flow and methodology development is an advantage
• RTL expertise (Verilog/System Verilog)
• Excellent debug and analytical skills
• Ability to work well in a collaborative environment with multi-disciplined teams

Minimum Skills:

• Bachelor’s degree in Electrical/Computer Engineering
• 2+ years of direct synthesis and physical design work experience
• Strong background in VLSI design, scripting
• Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools
• Hands on experience taping out designs in sub-micron technology node design

Preferred Skills:

• Master’s degree in Electrical/Computer Engineering
• 2+ years of direct synthesis and physical design implementation work experience
• In depth end to end experience from RTL2GDS, taping out at least 1-2 complex designs in deep sub-micron technology node

Minimum Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR
  Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
  OR
  PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.

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Pay range and Other Compensation & Benefits:

$133,600.00 - $200,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.