
Inventing the technologies the world loves.
Design Verification Lead – Peripheral IP Group (UVM) - Haifa, Israel
必备技能
Python
Linux
Company:
Qualcomm Israel Ltd.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Qualcomm’s Peripheral IP organization is looking for a hands‑on Design Verification Lead to drive verification of next‑generation wired/wireless peripheral subsystems that power Snapdragon platforms.
As a DV Lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute UVM‑based verification strategy, and lead a small team of talented engineers to first‑time‑right silicon.
This is a 5 days on site position in Haifa What you’ll do
-
Define verification strategy, test plan, and coverage goals for complex peripheral IP and subsystem blocks
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Architect, develop, and maintain UVM‑based constrained‑random verification environments
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Lead day‑to‑day activities of a small DV team: task planning, code and testplan reviews, mentoring, and technical guidance
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Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams
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Analyze and close functional and code coverage, drive quality metrics to tape‑out criteria
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Contribute to methodology and flow improvements across the Peripheral DV team
Minimum qualifications
-
BSc/MSc in Electrical/Computer Engineering or related field
-
At least 7 years of hands‑on verification experience using UVM and System Verilog
-
Strong background in digital design and SoC/IP architecture
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Proven technical leadership:
Prior experience leading or mentoring engineers or
-
Demonstrated ability and motivation to lead a small DV team (e.g., ownership of major IP, driving cross‑functional efforts)
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High technical proficiency in:
UVM testbench architecture (agents, sequences, scoreboards, coverage)
-
Constrained‑random, coverage‑driven verification
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Debugging complex failures in large‑scale regressions
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Scripting (Python/Perl/Tcl/shell) in a UNIX/Linux environment
Preferred qualifications
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Experience with high‑speed peripherals (e.g., USB, PCIe, Display, Ser Des, or similar I/O IP)
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Knowledge of low‑power, reset, and clock‑domain interactions at IP/SoC level
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Familiarity with regression management, metrics, and sign‑off criteria
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Experience working with global, cross‑site teams
What we offer
Opportunity to own verification of cutting‑edge peripheral IP used in high‑volume products
A strong technical environment with the ability to lead, influence, and mentor
Collaboration with world‑class design, architecture, CAD and validation teams
Growth path toward broader technical or managerial leadership within Qualcomm
If you are a technically strong verification engineer with deep UVM experience and the drive to lead people and projects, we’d like to hear from you.
To apply: Please submit your CV through the Qualcomm careers portal and reference “DV Lead – Peripheral IP Group” in your application.
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers.
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关于Qualcomm

Qualcomm
PublicInventing the technologies the world loves.
10,001+
员工数
San Diego
总部位置
$136B
企业估值
评价
3条评价
3.0
3条评价
工作生活平衡
3.0
薪酬
2.0
企业文化
2.5
职业发展
3.5
管理层
2.0
45%
推荐率
优点
Opportunity to work at reputable company
Interesting work and new skill development
Strong brand name recognition
缺点
Low compensation compared to market rates
Poor communication from employees
No benefits provided
薪资范围
21个数据点
Mid/L4
Mid/L4 · Analog Mixed Signal Design Engineer
4份报告
$155,284
年薪总额
基本工资
$119,434
股票
-
奖金
-
$155,284
$155,284
面试评价
8条评价
难度
2.8
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
常见问题
Coding/Algorithm
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
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