Company:

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

We are looking for a physical design engineer to join our design team in Tijuana. Successful candidate will be part of design group responsible to deliver IP implementation like high-speed DDR, USB, PCI, PLL and mixed Digital and Analog designs. This person should demonstrate extensive knowledge in physical design flow and methodologies to ensure high quality and timely release, successful silicon in nanometer technologies, understand key design challenges and solutions.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities:

• Provide technical leadership and direction to project execution.

• Manage project timelines, deliverables and track them to closure.

• Mentor, guide and help team members in a fast-paced environment.

• Collaborate with design team and work with cross functional teams.

• Use good verbal and written communication skills to describe daily technical and non-technical issues

• Take responsibility for your own work and making decisions

• Exercise creativity to troubleshoot technical problems

Requirements:

• Bachelor’s Degree or higher in Electrical Engineering, Computer Engineering, or related fields.

• A minimum of 6 years’ experience in physical design engineering

Successful Tapeouts in Nanometer Technologies:

• Understanding of complex foundry design rules and requirements

• In-depth knowledge of design flow RTL to GDS process

Floor-planning

Automatic and custom placement

• Multi-voltage power domains

• Pre-placement and pre-routing

• Power Design Networks PDN-planning

• Place & Route

• Clock Tree Synthesis and customization

• Static Timing Analysis

Understand Timing constraints:

• Fixing timing violations

• Physical Verification

DRC, LVS, ERC, DFM

• Virtuoso is a plus

• Experience with industry leading tools

Cadence

• Synopsys

• Mentor

• Ansys

• Working knowledge of programming languages, HDL, OS

Python, C++, TCL, Perl, Awk

• Verilog/VHDL,Unix/Linux

• Excellent written and verbal communication.

• Automation with Perl, Python and tcl is plus

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