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Job Title: Senior Design Verification Engineer / Location: Pune
Role Overview:
We are seeking an experienced Design Verification Engineer with 6+ years of expertise for execution of complex So Cs. The ideal candidate will have deep knowledge of ARM-based microcontrollers, low-power design verification, and experience with multiple interfaces and security IPs. This is a hands-on role requiring strong technical skills and collaboration in a fast-paced environment.
Key Responsibilities:
- Develop and own SoC-level and/or IP-level verification suites with coverage goals.
- Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
- Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
- Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage
- Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
- Familiar with both SoC-level and IP-level verification environments.
- Collaborate with the team in developing and improving flows for maximum reuse and efficiency.
- Mentor junior team members while actively collaborating with design teams for issue resolution and sign-off.
Required Qualifications:
- Experience: 5-12 years in SoC/IP verification with participation in successful tape-outs of So Cs.
- Technical Skills: Strong expertise in ARM-based microcontrollers and SoC-level verification, including C based DV.
- Proficiency in Verilog, System Verilog, UVM, and constrained-random verification.
- Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium).
- Experience with low-power verification (UPF) is a plus.
- Gate-level simulations and power-aware simulations is a plus.
- Good working knowledge of assertions (SVA) and functional coverage.
- Verification of multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI is desirable.
- Knowledge of Flash memory and security IPs is nice to have.
- Any experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage.
- Soft Skills: Comfortable working in a fast-paced environment.
- Strong team player with excellent communication skills.
- Education: Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering
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NXP Semiconductorsについて
NXP Semiconductors
PublicNXP Semiconductors produces secure connectivity solutions for embedded applications.
10,001+
従業員数
Eindhoven
本社所在地
$45B
企業価値
レビュー
3.7
10件のレビュー
ワークライフバランス
3.8
報酬
4.0
企業文化
4.2
キャリア
3.2
経営陣
3.0
72%
友人に勧める
良い点
Supportive management and colleagues
Good work-life balance and flexible hours
Innovation and interesting technology projects
改善点
Limited career advancement and training opportunities
Management communication and organization issues
Heavy workload and long hours during deadlines
給与レンジ
227件のデータ
Junior/L3
L3
Intern
Junior/L3 · Data Scientist
0件のレポート
$114,000
年収総額
基本給
$99,000
ストック
-
ボーナス
$15,000
$96,900
$131,100
面接体験
42件の面接
難易度
3.1
/ 5
期間
14-28週間
内定率
33%
体験
ポジティブ 69%
普通 13%
ネガティブ 18%
面接プロセス
1
Phone Screen
2
Technical Interview
3
Hiring Manager
4
Team Fit
よくある質問
Technical skills
Past experience
Team collaboration
Problem solving
ニュース&話題
NXP Semiconductors (NASDAQ:NXPI) Rating Lowered to "Strong Sell" at Mizuho - MarketBeat
MarketBeat
News
·
3d ago
Mizuho downgrades NXP Semiconductors stock on auto exposure - Investing.com
Investing.com
News
·
4d ago
Mizuho Securities Maintains NXP Semiconductors(NXPI.US) With Sell Rating, Maintains Target Price $188 - Moomoo
Moomoo
News
·
4d ago
This NXP Semiconductors Analyst Turns Bearish; Here Are Top 5 Downgrades For Friday - Benzinga
Benzinga
News
·
4d ago