採用
必須スキル
Verilog
SystemVerilog
Microarchitecture
SoC design
RTL design
Design verification
Timing analysis
Power analysis
Python
Perl
TCL
Leadership
Role Summary
We are seeking a highly accomplished Director of Engineering to lead** front-end design** of advanced So Cs, sub-systems optimized for AI inference, networking, and edge compute workloads.
This role requires a strong blend of hands-on technical depth,system-level thinking, and people leadership, driving silicon from concept through RTL, verification, physical design collaboration, and silicon bring-up—while optimizing performance, power, and efficiency.
Key Responsibilities
Microarchitecture Design
- Define and implement hardware architectures and micro-architectures optimized for AI inference performance, power efficiency, and scalability.
- Drive architectural trade-off analysis across compute, memory, interconnect, and I/O subsystems.
- Collaborate with system and software teams to align hardware architecture with AI workloads and inference use cases.
RTL Design & SoC / IP Integration
- Lead development and integration of RTL components using Verilog/System Verilog for IPs, sub-systems, and full So Cs.
- Oversee integration of internal and third-party IPs (ARM, RISC-V, PCIe, UCIe, USB, NoC, memory, AI accelerators).
- Ensure delivery of QC-clean RTL (Lint, CDC/RDC, UPF compliant) to backend teams.
Functional Verification & Design Quality
- Guide and review verification strategy, including testbench architecture, assertions, and coverage closure.
- Collaborate with verification teams on simulation-based, formal, and system-level verification.
- Ensure design robustness through early bug discovery and cross-functional debug.
People & Organizational Leadership
- Build, mentor, and lead high-performing teams across, RTL, and integration.
- Drive performance management, coaching, hiring, and technical career growth.
- Foster a culture of engineering excellence, accountability, and innovation.
Physical Design Collaboration & Silicon Readiness
- Partner closely with physical design teams on synthesis, timing closure, congestion, and power optimization.
- Provide front-end guidance for floorplan-aware RTL, clocking strategies, and low-power techniques.
- Support backend sign-off and silicon bring-up, ensuring first-silicon success.
Program Execution & Delivery
- Manage schedules, dependencies, and risks across global cross-functional teams.
- Deliver programs with high quality, predictable execution, and aggressive timelines.
Required Qualifications
Experience
- 15 years of experience in ASIC front-end design and SoC architecture.
- Proven delivery of complex So Cs / AI accelerators in production silicon.
- Strong background in architecture, RTL, verification, timing, power, and silicon bring-up.
Technical Skills
- Verilog / System Verilog, microarchitecture
- SoC/IP integration
- Performance and power modeling methodologies
- ASIC sign-off flows: Lint, CDC/RDC, STA, power analysis
- Low-power design: clock gating, power gating, DVFS
- Scripting: Python, Perl, TCL
Leadership Skills
- Strong system-level thinking and technical decision-making
- Ability to influence across organizations and geographies
- Excellent communication with executive and technical stakeholders
- Proven mentoring and team-building capability
総閲覧数
0
応募クリック数
0
模擬応募者数
0
スクラップ
0
類似の求人

Software Development Manager, Amazon Customer Service
Amazon · Hyderabad, TS, IND

Director – Engineering Systems, Tech & Reporting Lead
Amgen · India - Hyderabad

WFM IT Engineering Manager
TJX (TJ Maxx) · Hyderabad, TS 500081

WFM IT Engineering Manager - Integrations
TJX (TJ Maxx) · Hyderabad, TS 500081

Software Engineering Manager - HIH - Evernorth
Cigna · Hyderabad, India
NXP Semiconductorsについて
NXP Semiconductors
PublicNXP Semiconductors produces secure connectivity solutions for embedded applications.
10,001+
従業員数
Eindhoven
本社所在地
$45B
企業価値
レビュー
3.7
10件のレビュー
ワークライフバランス
3.8
報酬
4.0
企業文化
4.2
キャリア
3.2
経営陣
3.0
72%
友人に勧める
良い点
Supportive management and colleagues
Good work-life balance and flexible hours
Innovation and interesting technology projects
改善点
Limited career advancement and training opportunities
Management communication and organization issues
Heavy workload and long hours during deadlines
給与レンジ
227件のデータ
Junior/L3
L3
Intern
Junior/L3 · Data Scientist
0件のレポート
$114,000
年収総額
基本給
$99,000
ストック
-
ボーナス
$15,000
$96,900
$131,100
面接体験
42件の面接
難易度
3.1
/ 5
期間
14-28週間
内定率
33%
体験
ポジティブ 69%
普通 13%
ネガティブ 18%
面接プロセス
1
Phone Screen
2
Technical Interview
3
Hiring Manager
4
Team Fit
よくある質問
Technical skills
Past experience
Team collaboration
Problem solving
ニュース&話題
NXP Semiconductors (NASDAQ:NXPI) Rating Lowered to "Strong Sell" at Mizuho - MarketBeat
MarketBeat
News
·
3d ago
Mizuho downgrades NXP Semiconductors stock on auto exposure - Investing.com
Investing.com
News
·
4d ago
Mizuho Securities Maintains NXP Semiconductors(NXPI.US) With Sell Rating, Maintains Target Price $188 - Moomoo
Moomoo
News
·
4d ago
This NXP Semiconductors Analyst Turns Bearish; Here Are Top 5 Downgrades For Friday - Benzinga
Benzinga
News
·
4d ago