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Benefits & Perks
•Learning Budget
•Learning
Required Skills
Verilog
SystemVerilog
Python
Perl
Shell
Digital design
RTL
Job Summary:
We are seeking a highly motivated and detail-oriented Entry-Level SoC Verification Engineer to join our digital verification team. The ideal candidate will assist in verifying complex Automotive 5nm System-on-Chip (SoC) designs through simulation, emulation, and formal techniques. This is a great opportunity to work on cutting-edge semiconductor technologies and grow your career in hardware design and verification.
Key Responsibilities:
- Assist in developing and executing verification plans for SoC designs.
- Write and maintain testbenches using System Verilog/UVM or other verification methodologies.
- Perform simulation-based verification and debug test failures.
- Collaborate with design, architecture, and software teams to understand specifications and corner cases.
- Contribute to regression setup and automation of verification flows.
- Document verification results and provide feedback to design teams.
Required Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Strong understanding of digital design fundamentals (RTL, FSMs, timing, etc.).
- Familiarity with Verilog/System Verilog and simulation tools (e.g., VCS, Questa, or XSIM).
- Exposure to scripting languages (Python, Perl, or Shell) for automation.
- Good problem-solving and communication skills.
- Ability to work in a collaborative team environment.
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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About NXP Semiconductors
Reviews
3.9
44 reviews
Work Life Balance
3.8
Compensation
3.9
Culture
4.1
Career
3.6
Management
3.8
73%
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Pros
Competitive compensation and benefits
Good work-life balance and flexible environment
Interesting projects and challenges
Cons
Room for improvement in processes
Work-life balance varies by team
Internal communication could improve
Salary Ranges
267 data points
Junior/L3
L3
Junior/L3 · Data Scientist
0 reports
$114,000
total / year
Base
$99,000
Stock
-
Bonus
$15,000
$96,900
$131,100
Interview Experience
42 interviews
Difficulty
3.1
/ 5
Duration
14-28 weeks
Offer Rate
33%
Experience
Positive 69%
Neutral 13%
Negative 18%
Interview Process
1
Phone Screen
2
Technical Interview
3
Hiring Manager
4
Team Fit
Common Questions
Technical skills
Past experience
Team collaboration
Problem solving
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