Project Proposal: A 77GHz Continuous-Time SD ADC

Introduction

Future generation automotive receivers for eg FMCW MIMO radar reception require increasing larger bandwidths, higher dynamic range and spectral purity at low-power consumption. Moreover, a general trend is that the ADC is moving closer to the antenna, to reduce system complexity, lower cost and improve performance. This project focuses on the research and design of a continuous time SD ADC with embedded 77GHz mixer front-end for direct digitization and demodulation of the mmW FMCW signals.

Objectives

The objective of this project is the realization of a wideband, high dynamic range continuous-time ADC with embedded mmW mixer for direct 77GHz digitization. Voltage and current mixer concepts will be studied to meet the stringent noise and linearity requirements. There will be close cooperation with already running PhD projects on continuous-time ADCs so the focus of this project can be on the critical mmW input stage of the ADC, while potentially benefiting from re-use for the back-end stage design.

Background

Frequency‑modulated continuous‑wave (FMCW) radar has become the dominant sensing modality for automotive radar applications due to its robustness, high range resolution, and compatibility with compact CMOS implementations. In FMCW radar systems, distance and velocity information are extracted from the frequency difference between the transmitted chirp and the received echo, which places stringent requirements on receiver linearity, noise performance, and bandwidth. As radar systems evolve toward higher resolution and multi‑antenna (MIMO) configurations, the receiver front‑end must support increasingly wide instantaneous bandwidths while maintaining low power consumption and high dynamic range.

Modern FMCW radar receivers typically operate in the 76–81 GHz band and rely on down‑conversion of the received millimeter‑wave (mmW) signal to baseband. This function is performed by mmW mixers, which translate the high‑frequency input signal using a local oscillator (LO) derived from the same chirp generator as the transmitter. Mixer performance is critical, as it directly impacts receiver noise figure, linearity, and spurious response. Both voltage‑mode and current‑mode mixer topologies are commonly used at mmW frequencies, each presenting trade‑offs in terms of conversion gain, isolation, and compatibility with subsequent baseband circuitry. Implementing these mixers in advanced CMOS technologies enables high levels of integration but also exacerbates challenges related to device noise, parasitics, and LO leakage.

A key architectural trend in FMCW radar receivers is the push towards earlier digitizing, placing the analog‑to‑digital converter (ADC) closer to the antenna interface. Early digitization reduces the complexity of analog baseband processing, improves calibration capabilities, and facilitates digital beamforming in MIMO systems. However, this shift places stringent requirements on the ADC, which must handle wide signal bandwidths, large dynamic range, and strong interferers while operating at low supply voltages. Continuous‑time sigma‑delta (CT ΣΔ) ADCs are particularly attractive in this context due to their inherent anti‑alias filtering, high linearity, and excellent noise‑shaping properties.

Integrating a mmW mixer directly into a CT ΣΔ ADC represents a promising but challenging approach for next‑generation FMCW radar receivers. The mixer‑ADC interface must simultaneously satisfy conflicting requirements on noise, linearity, stability, and clocking, particularly at carrier frequencies around 76-81 GHz. Careful architectural choices and circuit‑level innovation are therefore required to realize a robust, low‑power solution capable of direct digitization and demodulation of FMCW radar signals. Key research challenges include the interaction between mm Wave mixing and continuous‑time ΣΔ feedback loops, LO phase‑noise, and stringent linearity constraints under FMCW chirp excitation. The project will explore architectural and circuit‑level innovations to address these challenges.

Requirements for this role

• Master’s degree in electrical engineering or related field

• Strong background in mmW and analog/mixed-signal circuit design

• Background in data converters

• Experience in Cadence and Matlab

Project Plan

• Phase 1: System architecture and behavioral modeling, define system specifications and performance targets.

• Phase 2: Circuit design and simulation.

• Phase 3: Layout, fabrication, and testing of prototype design.

• Phase 4: Publication and benchmarking.

This 4 years PhD project is a cooperation between Delft University of Technology and NXP Semiconductors. Interested in joining our team? Submit your CV and personal background and let us talk about it!

Supervisors:

Kofi Makinwa (Delft University)

Lucien Breems (NXP Semiconductors, Delft University)

Muhammed Bolatkale (NXP Semiconductors, Delft University)

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