As a Senior ASIC Design Methodology Engineer, you will help build the automation backbone for our next‑generation GPU memory subsystem as part of a long‑term investment in this area. You will lead IP modularization and design‑methodology efforts, design scalable flows, and apply AI‑driven automation to improve efficiency and reliability across multiple GPU programs, with room to grow your impact as the team and scope expand.

What you'll be doing:

• Lead the modularization of the GPU Memory Subsystem into clear, well‑defined compartments/units, ensuring robust and well‑specified interfaces between modules.

• Work with front‑end IP, integration, design, and verification teams on infrastructure, build, and flow topics, proactively resolving flow‑related issues across the design.

• Define and track metrics/KPIs to understand build dependencies between units/compartments and use these insights to drive flow and infrastructure improvements.

• Design, develop, and maintain tools and automation flows that reduce manual effort, improve team productivity, and support more complex GPU designs.

• Apply AI techniques (e.g. agents, prompt engineering, workflow orchestration) to diagnose issues, analyze logs, and enhance workflows.

What we need to see:

• Master’s degree or 2+ years equivalent experience in Electrical/Computer Engineering or a related field.

• Solid experience with build/flow automation and strong skills in industry‑standard scripting languages (e.g. Python, Perl, Makefile, or similar).

• Good understanding of ASIC/SoC concepts and front‑end design or verification flows, with a focus on automation, methodology, and efficiency.

• Proven experience in process automation or efficiency improvement, including identifying bottlenecks and proposing practical, data‑driven solutions.

• Good communication skills, strong spoken English, and the ability to collaborate effectively across teams.

Ways to stand out from the crowd:

• Experience building or using AI agents for engineering workflows, including prompt engineering and workflow orchestration.

• Familiarity with dependency management or foundational concepts in large hardware development projects.