You will realize next-generation packaging solutions by identifying, integrating, and validating novel materials. It is a highly cross-functional role, engaging RF/EM, mechanical/thermal, optical integration, reliability, supplier, and manufacturing teams. The ideal candidate brings a strong materials science and packaging background, hands-on process know-how, and a data-driven approach to reliability-by-design.

• M.S. or Ph.D in Materials Science/Engineering, Mechanical Engineering, Electrical Engineering, Physics, Chemistry or a related field, with 5+ years in microelectronics packaging.

• Hands-on experience with at least some of the following tools for package and system design (e.g., Cadence Allegro, Xpedition, Altium) and mechanical/thermal/EM simulation (e.g. Creo/Solidworks, Ansys Mechanical, FloTHERM/Icepak, HFSS, CST).

• Proficiency in characterization methods and failure analysis (Radiography, RF S-parameters, optical insertion loss, DMA/TMA, SEM, AFM, etc.)

• Experience with wafer-level and substrate fabrication processes and the ability to identify and de-risk new processes.

• Strong cross-functional collaboration and communication skills, with the ability to translate complex experimental data into clear design and process recommendations for both technical and non-technical stakeholders.

• Identify, integrate, and qualify novel materials into advanced microelectronics packages (e.g., dielectrics, interconnects, adhesives, TIMs, etc.).

• Drive package and test fixture design from architecture planning to CAD generation to system level validation, including mechanical, thermal, electrical, and optical design and accelerated reliability testing.

• Plan and execute material and package characterization and failure analysis.

• Collaborate with OSATs, Foundries, and material suppliers to validate new process flows and materials and identify and resolve failure mechanisms.

• Build data-backed acceptance criteria for novel materials and correlate lab measurements with modeling results to inform design trade-offs.