
Leading company in the technology industry
Principal Physical Design Engineer, HBM
必須スキル
Python
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Responsibilities:
- Lead end‑to‑end physical design for High Bandwidth Memory (HBM) base and memory dies from netlist through GDSII, including floorplanning, power planning, placement, clock tree synthesis, routing, and signoff.
- Define and drive HBM‑specific physical architecture, including channel partitioning, physical layer (PHY) placement, through‑silicon via (TSV) keep‑out regions, and die‑package co‑design alignment.
- Optimize bandwidth, latency, power, and yield through architecture‑level tradeoffs and collaboration with memory architecture, PHY, RTL, synthesis, design‑for‑test, and packaging teams.
- Lead power delivery network design and ensure IR drop, electromigration, and thermal closure across all operating modes.
- Oversee timing closure across corners for high‑speed logic and HBM PHY interfaces, addressing signal integrity, noise, and crosstalk.
- Ensure physical signoff readiness, including static timing analysis, IR/EM, signal integrity, design rule checks, layout versus schematic, density, and reliability compliance.
- Drive engineering change order strategies, flow improvements, automation, and methodology development for HBM physical design.
- Mentor engineers and serve as a key technical voice in tape‑out and executive design reviews.
Minimum Qualifications:
- Bachelor’s degree or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent professional experience.
- 12+ years of hands‑on experience in advanced‑node physical design with proven tape‑out experience in HBM, dynamic random‑access memory (DRAM), or large memory‑centric designs.
- Deep expertise in floorplanning, hierarchical physical design, timing closure, static timing analysis, power integrity (IR/EM), thermal analysis, and physical signoff.
- Expert‑level experience with Cadence Innovus and/or Synopsys ICC2 or Fusion Compiler, plus experience with Voltus, Red Hawk, or equivalent power integrity tools.
- Familiarity with Calibre design rule checking, layout versus schematic, and advanced foundry signoff flows.
Preferred Qualifications:
- Experience with HBM2E, HBM3, or HBM3E products and TSV‑based designs, including micro‑bump layouts.
- Knowledge of die‑to‑die interfaces, wide parallel buses, and advanced packaging such as 2.5D interposers and chiplets.
- Background in signal integrity considerations for dense, high‑speed memory designs.
- Strong Tcl or Python scripting skills for physical design flow automation.
- Experience supporting system‑level integration with graphics processing units, accelerators, or system‑on‑chips.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
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Micronについて

Micron
PublicMicron Technology is a global leader in memory and storage solutions, manufacturing DRAM, NAND flash memory, and solid-state drives for computing, mobile, automotive, and data center applications.
10,001+
従業員数
Boise
本社所在地
$100B
企業価値
レビュー
10件のレビュー
3.6
10件のレビュー
ワークライフバランス
2.8
報酬
3.5
企業文化
4.1
キャリア
2.7
経営陣
3.0
65%
知人への推奨率
良い点
Supportive management and great team culture
Excellent health benefits and compensation
Cutting-edge technology and interesting projects
改善点
Long hours and heavy workload
High pressure environment leading to burnout
Limited career advancement opportunities
給与レンジ
37件のデータ
Mid/L4
Mid/L4 · DESIGN ENGINEER
1件のレポート
$204,611
年収総額
基本給
$156,624
ストック
-
ボーナス
-
$204,611
$204,611
面接レビュー
レビュー4件
難易度
2.8
/ 5
期間
14-28週間
内定率
25%
体験
ポジティブ 25%
普通 25%
ネガティブ 50%
面接プロセス
1
Application Review
2
Recruiter/Phone Screen
3
Technical Interview
4
Final Round Interview
5
Offer
よくある質問
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
Past Experience
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