
Leading company in the technology industry
Design Verification Engineer - Early Career at Marvell
About the role
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Connectivity group is the industry leader in PHY devices for AI, cloud datacenter and enterprise infrastructure. Our devices today power the full range of network connectivity from the optics of the AI GPU boards to top of the rack optical fibers and active copper cables of the data centers and their fabrics. The Connectivity Verification Group works closely with Analog and Digital Design teams and Systems/DSP teams to incorporate and build models and testbench infrastructure for mixed signal designs and verify the digital and analog designs and micro-architectures against the system definition and requirements and also works closely with the Software team to set up the API building infrastructure and guidelines.
What You Can Expect
- Learn how the connectivity devices are dramatically impacting the AI-ML hardware revolution and the datacenters
- Learn the state-of-the-art optical PHY module architecture and design for 1.6T and 3.2T
- Learn state of the art UVM and System Verilog-based verification environment
- Apply the knowledge of Object-Oriented programming and its application to UVM/System Verilog to build new features into the verification environment as well as the test suite
- Work closely with Design teams to bring up new design features and verify them
- Learn modern day techniques of formal verification as well as code and functional coverage
What We're Looking For
- Bachelor's Degree in Electrical Engineering or a related field
- College level coursework on Digital Logic Design using Verilog, Computer Architecture, Signals, Systems and basic Digital Signal Processing
- Basic knowledge of Electrical Circuit Analysis (a course in Analog Circuits is preferred)
- A course project involving Object Oriented Programming language such as C/C++ or Java
- A course project involving principles of Verilog/VHDL/System-Verilog
Expected Base Pay Range (USD)
81,880 - 122,600, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
Required skills
SystemVerilog
UVM
Design verification
Mixed-signal concepts
PHY basics
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About Marvell

Marvell
PublicMarvell Technology, Inc. is an American company, headquartered in Santa Clara, California, which develops and produces semiconductors and related technology.
5,001-10,000
Employees
Santa Clara
Headquarters
$15.2B
Valuation
Reviews
10 reviews
4.0
10 reviews
Work-life balance
4.2
Compensation
3.5
Culture
4.1
Career
3.2
Management
3.4
75%
Recommend to a friend
Pros
Supportive team and leadership
Good work-life balance and flexibility
Collaborative and inclusive environment
Cons
Management issues and disorganization
Limited career advancement opportunities
High workload and stress
Salary Ranges
16 data points
Junior/L3
Junior/L3 · DATA SCIENCE AND ENGINEERING PROFESSIONAL II
1 reports
$111,800
total per year
Base
$86,000
Stock
-
Bonus
-
$111,800
$111,800
Interview experience
1 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Offer rate
100%
Experience
Positive 100%
Neutral 0%
Negative 0%
Interview process
1
Application Review
2
Recruiter Call
3
Technical Screen
4
Final Round Interview
5
Offer Decision
Common questions
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
UI/UX Design Principles
Latest updates
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News
·
2w ago