
Leading company in the technology industry
Senior Staff Engineer - Design Verification- SerDes/ PHY/AMS / Mixed‑Signal at Marvell
About the role
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Central Engineering AMS IP delivers high quality analog and mixed signal IP and verification for Marvell’s advanced IPs, So Cs and platforms. The team provides scalable, reusable solutions across high speed interfaces (Ser Des, DDR, D2D, PCIe, Ethernet PHY components) and advanced process nodes (5nm, 3nm, 2nm), enabling first time right silicon, reduced integration risk, and faster time to market through strong design verification convergence and system level validation.
What You Can Expect Education:
- Bachelor’s or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5 to 9 years of experience. in verification and/or AMS/mixed‑signal design environments.
**•**Strong hands‑on experience with System Verilog and UVM.
• Working knowledge of:
**• Ser Des or PHY architectures• AMS / mixed‑signal concepts• Register modeling and firmware interaction•**Experience integrating or using verification IPs (VIPs).
**•**Ability to debug issues across multiple abstraction layers with guidance.
• Familiarity with regression management and coverage analysis.
**Behavioral & Growth Expectations•**Demonstrates strong ownership of assigned verification areas.
**•**Executes tasks independently with attention to quality and detail.
• Communicates progress, issues, and technical findings clearly to the team.
**•**Actively seeks to deepen domain knowledge and technical breadth.
• Willingness to learn from senior engineers and accept feedback.
**•**Begins contributing beyond tasks by suggesting incremental improvements to testbenches, checks, or flows.
**Nice‑to‑Have / Growth Differentiators•**Exposure to AMS verification tools and modeling techniques.
**•**Experience with link training, calibration logic, or DSP‑analog interaction.
**•**Basic exposure to GLS, low‑power verification, or post‑silicon debug.
• Interest in automation, scripting, or productivity improvements.
What We're Looking For
The Staff Engineer is a hands‑on verification engineer responsible for driving block‑ and subsystem‑level verification of AMS and high‑speed Ser Des IPs. This role emphasizes execution excellence, technical rigor, and ownership, with opportunities to grow into broader technical leadership over time.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
Required skills
SystemVerilog
UVM
Design verification
SerDes
PHY
Mixed-signal
VIP integration
Debugging
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About Marvell

Marvell
PublicMarvell Technology, Inc. is an American company, headquartered in Santa Clara, California, which develops and produces semiconductors and related technology.
5,001-10,000
Employees
Santa Clara
Headquarters
$15.2B
Valuation
Reviews
10 reviews
4.0
10 reviews
Work-life balance
4.2
Compensation
3.5
Culture
4.1
Career
3.2
Management
3.4
75%
Recommend to a friend
Pros
Supportive team and leadership
Good work-life balance and flexibility
Collaborative and inclusive environment
Cons
Management issues and disorganization
Limited career advancement opportunities
High workload and stress
Salary Ranges
16 data points
Junior/L3
Junior/L3 · DATA SCIENCE AND ENGINEERING PROFESSIONAL II
1 reports
$111,800
total per year
Base
$86,000
Stock
-
Bonus
-
$111,800
$111,800
Interview experience
1 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Offer rate
100%
Experience
Positive 100%
Neutral 0%
Negative 0%
Interview process
1
Application Review
2
Recruiter Call
3
Technical Screen
4
Final Round Interview
5
Offer Decision
Common questions
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
UI/UX Design Principles
Latest updates
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