About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Come and join the excitement of developing world’s highest performance serial links!
Marvell’s Central Engineering Group is responsible for development of range of mixed signal IPs that support Marvell’s success in Datacenter, Networking, and ASIC businesses. From industry leading designs of high performance Ser Des and PHY, analog front ends to IPs such as ADC/DACS, temperature sensors and PLLs, Central Engineering group delivers the essential technology behind this success.

What You Can Expect

• The candidate will be working on analog design of high-speed and high-performance Ser Des in advanced technology nodes, 3nm, 2nm and beyond.

• Participate in Ser Des Architecture Development with DSP, Analog and Digital design teams.

• Work with the AE for the IP characterization and validation plan

• Product and customer supporting.

• Provide instructions to the layout engineers.

What We're Looking For

• PhD in Electrical Engineering or related fields.

• Strong analog design fundamentals and experience in designing analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed Ser Des blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).

• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must

• Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.

• Good understanding of analog layout optimization for high-speed designs

• Knowledge in system level pre-tape out analog validation

• Knowledge in silicon bring-up and debugging efforts

• Strong communication and documentation skills

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.