About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Senior Staff Architect, you will collaborate closely with domain experts across the silicon development spectrum and leverage your broad and deep experience to define and deploy the development environment that enables building the chips powering the next generation of Google Cloud systems. You will possess communication and collaboration skills, discover compelling solutions where others see ambiguity, and rally others to develop or deploy them.

In this role, you will work with silicon development teams and your peers in the Infrastructure, Tools, and Methodology team to architect, develop, and advocate the use of design tools and flows that speed the development of ground-breaking TPU, CPU, and networking chips and enable them to provide generational improvements in performance, power, and cost while enhancing reliability. You will weave your work into the deep tech stack of silicon design, composed of a mix of licensed electronic design automation (EDA) tools, custom tooling, and emergent technologies from core.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $240,000-$334,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Build productive relationships with thought leaders across programs to identify improvements, solicit feedback on proposals, and advocate methodology changes to enable convergence on a shared design environment.

• Leverage understanding of silicon development to architect and deploy a coherent system integrating first-party/third-party tools, industry-standard APIs, and scalable, design flows.

• Partner with Alphabet silicon teams, Deep Mind, and ecosystem leaders to ensure remains at the forefront of advanced development while contributing to broader industry progress.

• Ensure all developed technologies maximize project iteration speed while consistently achieving planned power, performance, cost, and quality metrics across the entire silicon portfolio.

• Guide teams in applying procedural and AI-first approaches to improve development efficiency and produce natural user interactions with next-generation design technologies.

Minimum qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience in technical leadership focusing on one or more critical aspects of silicon design.

• Experience in three or more silicon disciplines, including architecture modeling, logic design, functional verification, synthesis, timing analysis, DFT, or firmware development.

• Experience in developing, and deploying advanced tools and development flows that streamline the silicon lifecycle and improve engineering productivity.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 20 years of experience in advanced silicon development.

• Experience in identifying silicon methodology changes, architecting a solution, and advocating deployment with impact developers.

• Experience driving internal or external standardization efforts by defining solutions that bridge knowledge gaps among collaborators.

• Understanding of both front-end (e.g., architecture, logic design, verification) and back-end (e.g., logic synthesis, place-and-route, timing convergence, physical verification).

• Ability to leverage abstraction across multiple silicon domains, creating generalized solutions that drive architectural agility and enhance scalability for next-generation hardware projects.