Review chip specifications and designs, developing integration plans with software and system partners while coordinating hardware/software delivery.

Lead the bringup of ML compute features, integrating and validating complex hardware/software designs, including third-party IPs. Develop validation firmware to verify hardware functionality.

Execute hardware-software co-simulation methodologies leveraging RTL, emulation, and field-programmable gate array (FPGA) environments. Utilize architectural simulators and performance models to correlate results.

Design validation tests and microbenchmarks to verify IP functionality and performance. Author comprehensive test plans in coordination with cross-functional teams including Design, Design Verification (DV), Firmware, and Architecture.

Own debug discussions with Design/DV/Software/Architecture teams and help root cause functional failures and performance issues throughout the product development cycle. Improve validation coverage and sign-off processes for high-quality tapeout and production deployment.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

5 years of experience in at least two of the following: computer architecture, embedded firmware, ASIC design or verification, or the integration and enablement of first/third party IPs.

Experience in hardware/software integration and validation.

Experience with register-transfer level (RTL) development, design verification, and evaluation.