About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Define and drive low power solutions for Google So Cs to optimize Power Performance Area (PPA) under peak current and thermal constraints.

• Define power Key Performance Indicator (KPIs) and SoC/IP-level power goals, guide architecture, design and implementation to achieve power goals, and track power throughout the design cycle.

• Propose and drive power optimizations throughout the design process from concept to mass productization.

• Perform algorithm development, modeling and analysis of various low power approaches. Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.

• Model SoC and IP-level power and perform power rollups. Perform post-silicon characterization and productization of power features.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 4 years of experience with ASIC power management or low power design/methodology.

• Experience with ASIC low power flows and power management concepts.

Preferred qualifications

• Master's degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.

• Experience with low power architectures and optimization techniques (e.g., multi Vth/voltage domain design, clock gating, power gating).

• Experience with one or more of the following areas, such as ASIC power modeling and estimation, defining power goals, power management IP and sensors, peak power management/detection/mitigation, in-rush current, adaptive clock distribution.

• Experience with full product delivery cycle, Power Management Integrated Circuit (PMIC), Switched-Mode Power Supply (SMPS), Low-Dropout Regulator (LDO) and power delivery networks.