About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Package Design Lead Engineer, you will develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance substrate designs. The goal is to optimize package substrate design for electrical performance, reliability, and assembly. You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation.

Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline. This contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Physical package substrate design of large form-factor package for ML High-Performance Computers (HPCs).

• Develop and implement the methodology and Computer Aided Design (CAD) flow for efficient substrate design and enhanced productivity.

• Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.

• Collaborate closely with Signal integrity (SI)/Power Integrity (PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.

• Define and document the requirements for the package substrate design and Bill of Materials (BOM).

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of industry experience in chip package design/layout using Cadence APD or Mentor Expedition.

• Experience in chip package substrate layout, design verification, Design for Manufacturing (DFM) and taping out for production.

• Experience in design automation and scripting.

Preferred qualifications

• Experience in large-scale 2.5D/3.5D advanced package design.

• Experience in working with cross-functional teams including chip design, SI/PI, and Printed Circuit Board (PCB) design teams.

• Experience in physical verification flow (Layout Versus Schematic (LVS), Design Rule Check (DRC), Connectivity).

• Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD).

• Excellent leadership and project management skills.

• Excellent scripting skills to customize elements of the Cadence or Mentor workflow.