Define and drive to the implementation of physical design SoC Floorplan methodologies.

Take ownership of Floorplanning of one or more level.

Drive to the closure of Floorplanning of Subsystem (SS) or top level.

Contribute to design methodology, libraries, and code review.

Define the physical push down methodologies for the physical design engineers.

Bachelor’s degree in Electrical Engineering or equivalent practical experience.

8 years of experience with advanced design, including clock or voltage domain crossing, Design for Testing (DFT), and low power designs.

Experience with System on a Chip (SoC) cycles.

Experience in high-performance, high-frequency, and low-power designs.