Develop architectural and micro architectural models to enable quantitative analysis.

Conduct performance and power analyses and quantitatively evaluate proposals.

Contribute to Machine Learning workload characterization, benchmarking, and hardware-software co-design.

Collaborate with partners in hardware design, software, compiler, Machine Learning (ML) model and Research teams for hardware/software codesign.

Propose capabilities and next-generation TPUs and chip roadmap, and contribute to TPU chip specifications.

PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience

Experience in any one domain of computer engineering or silicon engineering through internships, academic research, or publications (e.g., co-design, digital design, architecture).

Experience programming in C++.