Participate in the physical design of blocks.

Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.

Collaborate with internal logic and internal and external teams to achieve the best power/performance analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

2 years of experience with physical design (e.g., from RTL to GDSII, including key stages like floor planning, place and route, and timing closure).

Experience in Python, Tcl, or Perl scripting.