Deliver compiler parallelization features and optimization techniques for TPU backend necessary for large-scale workloads.

Contribute to collective operation lowering/implementation on TPU platform.

Develop compiler optimization techniques at lower level and throughout the compiler stack.

Analyze upcoming and existing features in TPU architectures and leverage them for most optimal horizontal scaling performance.

Collaborate with ML Performance and research teams on achieving roofline performance for the most critical workloads. Build compiler related tools for debugging and preventing scaling issues and improving engineering experience.

Bachelor’s degree or equivalent practical experience.

2 years of experience with coding in C++, or 1 year of experience with an advanced degree.

1 year of experience with low-level programming.

1 year of experience working with hardware.