Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.

Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.

Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.

Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.

Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.

Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.

Experience in RTL verification and Gate Level Simulation (GLS) workflows.