About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Package CAD Engineer, your role is to develop design flow and automation for package substrate designs of advanced (2.5D/3.5D) packaging technologies and signal/power integrity for ML chips. This involves collaborating with SI/PI, package technologist, physical design and DFM to create complex, high-performance IC package designs.

You will manage the design and sign off flow and methodology set up for the ML IC packages. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline. This contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) & power.

Our team is responsible for designing and building the custom hardware, software, and networking technologies that power all of Google's services, as standard off-the-shelf hardware cannot meet our immense and unique computational needs. As a Hardware Engineer for ASIC, you are central to developing and building the systems that form the core of the world's largest and most powerful computing infrastructure. Your work spans from the fundamental levels of circuit design up to large-scale system design, seeing systems through to high-volume manufacturing, which directly influences the machinery in our cutting-edge data centers and impacts millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Be able to physically package design flow of large form-factor packages for ML High-Performance Computers (HPCs).

• Develop and implement the methodology and CAD flow for efficient substrate design, quality improvement, and enhanced productivity.

• Collaborate closely with SI/PI, thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.

• Design library setup and enable modular design.

• Automate SI/PI modeling flow and close collaboration with physical designers and SI/PI engineers.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• Experience in chip package substrate layout, optimization, design verification, DFM and taping out for production.

• 5 years of experience with chip package design/layout using Cadence APD or Mentor Expedition.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience in physical verification flow (LVS, DRC, connectivity).

• Experience with CAD for creating simple mechanical drawings, such as Package Outline Drawings (POD).

• Knowledge of and direct experience in large-scale 2.5D/3.5D advanced package design.

• Programming skills (Python, C++, MATLAB, etc.) to develop automation flow for SI/PI modeling and sign off.

• Proficiency in SKILL language for APD/Allgegro automation.