Establish and maintain cross-organizational alignment on TPU hardware, TPU compiler, TPU systems hardware, software co-design simulator compiler technology for state-of-the-art tech stack, velocity, quality of results and verifiability.

Develop compiler infrastructure for co-design simulator technologies to continuously keep up with evolving new system architecture choices and new ML workloads as well as supporting simulations at different abstraction levels.

Explore and define future ML accelerator system and chip architecture with objective and data-driven ground truth while strategizing collaboration across partner organizations to maximize adoption and impact.

Enable the cost effective peak performance of future ML systems with full-stack ML hardware, software co-design.

Establish understanding of the latest business-critical ML models (large-language models, large embedding models etc.) to inform optimizations of model architecture, software systems and hardware architecture.

Bachelor's degree or equivalent practical experience.

8 years of experience in software development.

7 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging.

5 years of experience with design and architecture; and testing/launching software products.