Plan the formal verification strategy and create the properties and constraints for digital design blocks.

Utilize formal property verification tools combined with formal verification closure techniques to verify properties.

Resolve difficulty to verify properties, and contribute improvements to methodologies to enhance formal verification results.

Implement reusable formal verification components.

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

8 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.

Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).