About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design Verification Engineer, you will work as part of a research and development team, and will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification.

You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.

• Create and enhance constrained-random verification environments using System Verilog/UVM, or Specman.

• Identify and write all types of coverage measures for stimulus and corner-cases.

• Debug tests with design engineers to deliver functionally correct design blocks.

• Lead coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 3 years of experience verifying digital logic at RTL level using System Verilog, or Specman/E for FPGAs or ASICs.

• Experience creating and using verification components and environments in standard verification methodology.

• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Preferred qualifications

• Master’s degree in Electrical Engineering, Computer Science, or a related field.

• Experience with UVM, System Verilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).

• Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).