Define end-to-end SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.

Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.

Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.

Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.

Drive organizational consensus on feature ROI and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

10 years of industry experience in Power Management or Low-Power Design/Methodology.

Experience navigating the full product delivery cycle, from initial architecture definition through post-silicon productization.

Experience with low-power architectures and power optimization techniques.