About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will help build the Security Operation Centers (So Cs) that power these data centers by developing and deploying test solutions with Automatic Test Equipment (ATE) for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSATs). This is an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generations of chips. You will drive ATE manufacturing testing to validate performance and screen bad devices. You will own all aspects of ATE testing, including wafer-sort, Final Test, and Burn-in, and work with cross-functional teams to ensure the optimal test coverage in production to ensure quality So Cs.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Test Chip ATE Hardware (HW)/Software (SW) bring-up and collaborate with foundries and design teams to correlate ATE results with original simulation models.

• Lead the development of Probe Cards and Load Boards, ensuring signal integrity through schematic entry and guided PCB layout.

• Enhance ATE platforms (V93K, UltraFLEX) using Python, C++, and Perl for automated test flows and pattern generation.

• Implement advanced routines, including Shmoo plots and Vmin/Vmax analysis to identify process marginalities and characterize performance across corners.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 2 years of experience in test chip design or product engineering.

• 2 years of experience with industry-standard tools, languages and methodologies used in the development of silicon-based Integrated Circuits (ICs) and chips.

• Experience in ATE test development for New Product Introduction (NPI) or High Volume Manufacturing (HVM).

Preferred qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 8 years of experience in test chip design or product engineering.

• Experience in testing Process Control Monitors (PCM), SRAM bit cells, Ring Oscillators, or thermal diodes.

• Experience with bench equipment (e.g., Oscilloscopes, Logic Analyzers) for debugging ATE-to-Device interactions.

• Knowledge of Design for Test (DFT) techniques, including Scan (ATPG), MBIST, and JTAG/IEEE 1149.1.

• Understanding of testing methodologies for High-Speed I/O (e.g., Ser Des, PCIe, DDR), PLLs, or ADCs/DACs.