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ASIC Design Verification Engineering Technical Leader
San Jose, California, US
·
On-site
·
Full-time
·
3w ago
必須スキル
Python
Linux
The application window is expected to close on: 05/22/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
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Participate in the ASIC design verification for Cisco high-end switching products.
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Lead, architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.
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Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.
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Construct testbenches components like scoreboard, agents, sequencers, and monitors.
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Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration and customer failures.
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Ensure comprehensive verification coverage through code and functional coverage implementation and review.
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Participate in and contribute to chip architecture definition and discussions.
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Mentor junior engineers on performing project tasks and problem solving.
Minimum Qualifications
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Bachelor’s degree in Electrical or Computer engineering and 10+ years of ASIC Design and Verification experience or Master’s degree in Electrical or Computer engineering and 8+ years of ASIC Design and Verification experience.
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Experience with ASIC design and verification processes (with System Verilog), debugging, methodology, and tools.
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Experience in leading the verification methodology (in UVM) of clusters/subsystems or full chip level for ASIC.
Preferred Qualifications
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Prior people management experience.
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Dashboard management for regression, coverage, test list completion and other DV statistics.
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Post-silicon lab bring-up experience.
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Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS
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Experience with Linux, C/C++, and/or Python/Perl.
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Experience in Networking.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
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10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
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1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
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Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
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Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
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80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
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Additional paid time away may be requested to deal with critical or emergency issues for family members
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Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
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.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
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1.5% of incentive target for each 1% of attainment between 50% and 75%;
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1% of incentive target for each 1% of attainment between 75% and 100%; and
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Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$183,800.00 - $303,100.00
Non-Metro New York state & Washington state:
$163,600.00 - $269,800.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
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Ciscoについて

Cisco
PublicCisco Systems, Inc. is an American multinational technology conglomerate corporation that develops, manufactures, and sells hardware, software, telecommunications equipment and other high-technology services and products focused on networking, cyber security and AI.
10,001+
従業員数
San Jose
本社所在地
$317B
企業価値
レビュー
4.3
10件のレビュー
ワークライフバランス
3.2
報酬
4.1
企業文化
4.5
キャリア
3.7
経営陣
3.8
78%
友人に勧める
良い点
Great team culture and supportive colleagues
Flexible hours and remote work options
Excellent benefits and competitive compensation
改善点
High-pressure and demanding work environment
Work-life balance challenges
Limited career advancement opportunities
給与レンジ
0件のデータ
L2
L3
L4
L5
L6
L2 · Business Analyst L2
0件のレポート
$70,294
年収総額
基本給
$28,118
ストック
$35,147
ボーナス
$7,029
$49,206
$91,382
面接体験
4件の面接
難易度
3.0
/ 5
期間
14-28週間
体験
ポジティブ 0%
普通 25%
ネガティブ 75%
面接プロセス
1
Application Review
2
Phone Screen
3
Technical Interview Round 1
4
Technical Interview Round 2
5
Behavioral Interview
6
Team Matching
7
Final Round
よくある質問
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
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